1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a semiconductor memory device and an access method therefor and, more particularly, to an asynchronous pseudo SRAM which uses a DRAM (Dynamic Random Access Memory) or ferroelectric memory in the memory core portion and an access method therefor.
2. Description of the Related Art
Pseudo SRAMs are commercially available, which use a DRAM or ferroelectric memory in the memory core portion to increase the degree of integration while maintaining use compatibility to existing SRAMs. In recent years, a demand for pseudo SRAMs oriented for cellular phones is increasing. Especially, a demand for asynchronous pseudo SRAMs which operate even asynchronously to an external input signal is growing.
To implement an asynchronous pseudo SRAM, an operation as shown in the timing charts of FIGS. 1A and 1B is necessary. FIG. 1A shows a read operation. FIG. 1B shows a write operation.
To realize the read and write operations shown in FIGS. 1A and 1B, an arrangement shown in FIG. 2 can be used. This arrangement has a plurality of ATDs which detect address transition. Address transition is detected by these ATDs. On the basis of an AND signal ATDSUM of the detection results, an internal chip enable signal (internal circuit control signal) INCE that controls the internal circuits is generated. Time-series signals that drive a word line WL and plate line PL are generated from the internal chip enable signal INCE to control the internal circuits.
More specifically, as shown in FIG. 2, a row address signal ADx output from a row address buffer circuit 101 and a column address signal ADy output from a column address buffer circuit 102 are supplied to an ATD circuit (address transition detection circuit) 100 so that the transitions of row and column addresses are detected. On the basis of the AND signal ATDSUM of the detection result by the ATD circuit 100, the internal chip enable signal INCE that controls the internal circuits is generated by an internal CE control circuit 103. An external chip enable signal /CE is supplied to the internal CE control circuit 103 to control the operation of the row address buffer 101 and column address buffer 102. The internal chip enable signal INCE generated by the internal CE control circuit 103 is supplied to a row system circuit 104 and column system circuit 105. Time-series signals that drive the word line WL and plate line PL in a memory cell array 106 are generated to control the data read and write (Dout and Din) operations.
A ferroelectric memory or DRAM is a destructive read memory. This memory requires an operation for returning data in a sense amplifier to a memory cell and rewriting the data after data access. Especially, in a ferroelectric memory (to be described later in detail), “1” and “0” data must be separately rewritten.
Hence, the address cannot be changed during the operation cycle. An address must be input complying with the TRCmin rule. In addition, to prevent any internal data destruction or error, an address that is input outside this rule is neglected.
To the contrary, an SRAM is a nondestructive read memory. It has no rule about the address input timing in a read mode. An output is obtained in accordance with an address that is input at an arbitrary timing.
For this reason, the conventional destructive read memory cannot be completely compatible with the SRAM in terms of operation.
To solve this problem, for example, Jpn. Pat. Appln. KOKOKU Publication No. 07-70214 (patent reference 1) discloses a semiconductor memory device. In this device, if the address continuously changes at a short time interval, and the second address change occurs before the internal operation based on the first address change is ended, the pieces of information of the second and subsequent address changes are temporarily stored in the device. With this arrangement, the internal operation corresponding to the second and subsequent address changes can be started after the internal operation according to the first address change is completed.
Jpn. Pat. Appln. KOKAI Publication No. 2002-150768 (patent reference 2) discloses a semiconductor memory device having a latch timing control circuit. The latch timing control circuit stores information representing a change in address signal during the operation of the core circuit. After the operation of the core circuit is ended, the control circuit causes a latch circuit to latch the changed address signal.
In both patent references 1 and 2, address buffers must always be set in an operative state to detect a change in address during the cycle operation. The address buffers must convert an external input signal of TTL or LVTTL level into a MOS level, i.e., the level of the internal power supply. To do this, a small current is always supplied to the address buffers. In addition, about 20 address buffers are simultaneously operating. Hence, if these address buffers are always set in the operative state, power consumption increases. A device for a cellular phone particularly requires low power consumption. For this reason, a semiconductor memory device which has low power consumption and is compatible to an asynchronous SRAM in terms of operation needs to be implemented.
In the embodiment of patent reference 1, all address transitions are received, and internal operations corresponding to them are executed. Hence, if an operation cycle starts in accordance with erroneous data, the next operation cycle cannot start until that cycle is ended. For this reason, processing must wait for a time corresponding to at least one cycle until the correct operation cycle starts. In the worst case, processing must wait for time corresponding to several cycles until correct data is input.
On the other hand, in the arrangement of patent reference 2, an address change during the cycle operation is latched in advance. After the end of the operation of the core circuit, the latch circuit latches the changed address signal. The next cycle is started by using that address signal. In this arrangement, if the address further changes after the end of the operation of the core circuit, the device cannot immediately cope with it. Data corresponding to the address is read out with a delay of at least one cycle.